The present invention generally relates to devices for measuring the bandwidth consumption of bus masters in a CPU-based system, and more particularly to a bus bandwidth consumption profiler which counts bus cycles owned by the bus masters over a period of time and simultaneously stores the number of owned bus cycles for output to the system to permit calculation of bus bandwidth consumption.
In a variety of CPU-based systems, a microprocessor communicates with memory devices over a communications bus. The microprocessor and other such bus masters, including the system UART, ethernet controller, etc., may function as data producers by placing data on the bus for storage in the memory devices (bus slaves), or as data consumers by removing data placed on the bus by the bus slaves. Either way, access to the bus by the bus masters is typically controlled by a bus arbiter which ensures that only one bus master drives the bus at any given time to avoid short circuits and damage to the system components.
More specifically, bus masters communicate over the bus by setting up a data transaction with the bus arbiter, executing the transaction, and acknowledging its conclusion. The amount of time (or number of clock cycles) a bus master has ownership of the bus during a given time period is proportional to the bus bandwidth consumption of that bus master. Between data transactions, dead time is provided to prevent two bus masters from simultaneously owning the bus. Accordingly, at least one dead cycle is typically required for every data transaction. As is well known in the art, the efficiency of the bus in terms of data transferred per unit time is decreased by each dead cycle. Since various bus masters are designed to transfer data at various data rates, a theoretical maximum efficiency exists for a given system of bus masters. If the clock speed (or frequency) of the bus is faster than the speed corresponding to maximum efficiency for the system, then the clock speed should be reduced to reduce power consumption. Accordingly, the more precisely the bandwidth consumption of the bus masters can be determined, the lower the system clock speed can be while maintaining the same throughput.
Conventional systems employ hard-wired logic circuits to measure bus bandwidth consumption. These circuits may also be incorporated in a system feedback loop to adjust the system clock speed in response to dynamic changes in bandwidth consumption. Such hardware-based systems, however, are undesirable for a variety of reasons. Clock frequency in hardware systems without bandwidth consumption feedback is based solely on estimates of the bandwidth consumption of the various bus masters. If the estimates are overly conservative (i.e., the clock frequency is higher than necessary to accommodate the desired throughput), then the entire chip design is undesirable because it consumes excessive power. Even hardware systems which incorporate bandwidth consumption feedback and clock speed adjustment are deficient because the intelligence used to adjust the clock speed is hard-wired and incapable of being adapted to different applications.
The present invention provides a bus bandwidth consumption profiler for measuring and reporting bus cycle utilization in a computer system having multiple bus masters and a bus arbiter for granting the masters ownership of the bus. In one embodiment, the profiler includes multiple master counters and a realtime counter. The master counters are individually paired with the bus masters to count cycles of bus ownership by their corresponding bus master. The realtime counter counts all bus cycles that occur during a time period ending with a profile event. Depending upon the profiler architecture, the profile event may occur when the realtime counter reaches its maximum count value (roll-over), or when the computer system provides a read signal to the profiler. When either profile event occurs, the current cycle counts of the master counters are simultaneously stored for output to the system. The realtime counter count is either known when the profile event is a realtime counter roll-over, or is stored at the time the cycle counts of the master counters are stored. A system designer may access these snap-shots of bus utilization to determine bus bandwidth consumption of the bus masters and tailor the system clock frequency to the desired system throughput, thereby minimizing system power consumption. The profiler may also be used in a system feedback loop to permit dynamic adjustment to the system clock frequency according to algorithms stored in the system CPU.
In another embodiment, the profiler uses fewer master counters than the number of bus masters in the system. Each master counter is configurable to count bus cycles owned by a selected master. A total counter may also be provided to count the combined bus cycles owned by all bus masters. Upon the occurrence of a profile event, the count data of the master counters, the total counter, and the realtime counter is simultaneously determined. Accordingly, the bus bandwidth consumption of the selected masters, as well as of the combined, non-selected masters, can be calculated using a reduced number of counters. This embodiment may likewise be employed as a design tool or as a bandwidth consumption monitoring device in a clock frequency correction feedback loop.